In the early part of the 5160's POST (Power On Self Test), the POST generates "checkpoint" codes.
The checkpoint codes were intended for IBM's use - to assist them diagnosing a faulty motherboard, probably at the time of manfacture.
There are four codes: 1, 2, 3, 4
Code 4 is only produced if there is a failure in early RAM (16 KB for early BIOS revisions, 64 KB for later BIOS revisions).
Sent with code 4 (code 04) is the failing bit pattern. E.g. if the bit pattern is 80, what is sent is an endless repeating pattern of 04/80/04/80/04/80/04/80 ...
The POST sends the codes to I/O port 60h (0x60).
Most POST cards can't read the codes because the cards typically monitor I/O port 80h (the diagnostic port used in the IBM AT), not 60h.
Data written to I/O port 60h is decoded by the 8255 PPI chip on the 5160 motherboard.
What did IBM use to view the codes ?
I do not think that IBM used a POST card, one monitoring I/O port 60h. Why? Because the POST does something that is not required if only a POST card was used:
Step 1: Sets the 8255 PPI's port A operation to output mode; then
Step 2: Disables output from the keyboard shift register (see here); then
Step 3: Sends checkpoint codes; then
Step 4: Reverts the 8255 PPI's port A operation to input mode; then
Step 5: Enables output from the keyboard shift register.
Because of steps 1 and 2, the checkpoint codes appear on port A of the 8255 PPI chip.
I can see them there using a logic state analyser - photo of observation here.
Why did IBM need the checkpoint codes to appear on port A of the 8255 PPI chip?
Maybe IBM's checkpoint viewing device attached to the 8255 PPI chip (via an IC clip), monitoring the port A pins.